Enhancement-Mode GaN MOSFET with Low Leakage Current and Improved Reliability

ABSTRACT

An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO 2 /Si 3 N 4  gate insulation layer on an AlGaN (or InAlGaN) barrier layer. The Si 3 N 4  portion of the SiO 2 /Si 3 N 4  gate insulation layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer, while the SiO 2  portion of the SiO 2 /Si 3 N 4  gate insulation layer significantly reduces the leakage current.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to GaN MOSFETs and, more particularly, toan enhancement-mode MOSFET with low leakage current and improvedreliability.

2. Description of the Related Art

GaN MOSFETS are well known in the art, and are of utilized in highpower, high frequency, and high temperature applications. GaN MOSFETSare typically based on the formation of a heterojunction between a GaNregion, typically known as the channel layer, and an overlying AlGaNregion, typically known as a barrier layer. The GaN channel layer andthe AlGaN barrier layer have different band gaps that induce theformation of a two-dimensional electron gas (2DEG) that lies at thejunction between the

GaN channel layer and the AlGaN barrier layer and extends down into theGaN channel layer.

The 2DEG, which functions as the “channel” of the transistor, produces ahigh concentration of electrons which causes a conventionally-formed GaNMOSFET to function as a depletion-mode device (nominally on when zerovolts are applied to the gate of the device, and the source and drainregions of the device are differently biased).

Although there are applications for depletion-mode GaN MOSFETs, thenominally on state of a depletion-mode transistor requires the use of acontrol circuit during start up to ensure that source-to-drainconduction within the transistor does not begin prematurely. On theother hand, an enhancement-mode GaN MOSFET (nominally off when zerovolts are applied to the gate of the device, and the source and drainregions of the device are differently biased) does not require a controlcircuit because the transistor is nominally off at start up when zerovolts are placed on the gate.

However, to form an enhancement-mode GaN MOSFET, the AlGaN barrier layermust be made thin enough (e.g., a few nm thick) so that when zero voltsare applied to the gate of the device, (and the source and drain regionsof the device are differently biased) substantially no electrons arepresent in the 2DEG region, and when a voltage that exceeds a thresholdvoltage is applied to the gate of the device, (and the source and drainregions of the device are differently biased), electrons accumulate inthe 2DEG region and flow from the source region to the drain region.

One problem with reducing the thickness of the AlGaN barrier layer isthat high levels of leakage current can pass through the AlGaN barrierlayer to the gate, which is conventionally implemented as a Schottkycontact. One solution to this problem is to add a gate insulation layerthat lies between the AlGaN barrier layer and the gate.

Current-generation, enhancement-mode GaN MOSFETs use a variety ofdeposited oxides to form the gate insulation layer. These depositedoxides include Al₂O₃, HfO₂, MgO, Gd₂O₃, Ga₂O₃, ScO₂, and SiO₂. Of all ofthese oxides, SiO₂ has a bandgap Eg of 9 eV and a ΔEc to AlGaN that canbe as high as 2.5 eV, thereby leading to the lowest leakage current anda threshold voltage as high as 2.5 volts.

One problem with all of these deposited oxides, including SiO₂, is thatthese deposited oxides have a high density of interface states (e.g.,greater than 4×10¹¹/cm²) that results in a large number of trappingsites at the junction between the gate insulation layer and the AlGaNbarrier layer. Large numbers of trapping sites lead to the breakdown ofthe gate insulation layer which, in turn, reduces the long-termreliability of the GaN devices. Thus, there is a need for anenhancement-mode GaN MOSFET that has a low leakage current.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-4 are a series of cross-sectional views illustrating an exampleof a method of forming an enhancement-mode GaN MOSFET 100 in accordancewith the present invention.

FIGS. 5-9 are a series of cross-sectional views illustrating an exampleof a method of forming an enhancement-mode GaN MOSFET 500 in accordancewith an alternate embodiment of the present invention.

FIG. 10 is a band diagram illustrating the leakage current in accordancewith the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1-4 show a series of cross-sectional views that illustrate anexample of a method of forming an enhancement-mode GaN MOSFET 100 inaccordance with the present invention. As described in greater detailbelow, the method of the present invention forms a SiO₂/Si₃N₄ gateinsulation layer on an AlGaN barrier layer (or optional InAlGaN barrierlayer) which significantly reduces the formation of interface states atthe junction between the gate insulation layer and the barrier layer.Reducing the density of interface states significantly reduces thenumber of trapping sites which, in turn, improves the long-termreliability on the GaN devices.

As shown in FIG. 1, the method of the present invention utilizes aconventionally-formed semiconductor substrate 110. Substrate 110 can beimplemented as an insulating substrate or with a highly resistivematerial such as silicon (e.g., <111>), sapphire, or silicon carbide. Asfurther shown in FIG. 1, the method of the present invention begins byforming an epitaxial layer 112 on substrate 110. Epitaxial layer 112,which is formed in a metal organic chemical vapor deposition (MOCVD)reactor using a conventional process, includes an undoped AlGaN bufferlayer 114, an undoped GaN channel layer 116, and an undoped or n-dopedAlGaN barrier layer 118 (or optionally an undoped or n-doped InAlGaNbarrier layer 118). The AlGaN buffer layer 114, in turn, includes anumber of undoped AlGaN layers with different aluminum compositions thatare used to mitigate stress.

As shown in FIG. 2, in accordance with the present invention, afterepitaxial layer 112 has been formed, a Si₃N₄ layer 120 is epitaxiallygrown on the AlGaN barrier layer 118 directly in the same MOCVD reactoras the AlGaN barrier layer 118 using SiH₄ and NH₃. In other words, theSi₃N₄ layer 120 is epitaxially grown after the AlGaN layer 118 is grownwithout removing the structure with the AlGaN layer 118 from the MOCVDreactor.

The Si₃N₄ layer 120 is preferably grown to have a thickness ofapproximately 10-100 nm, with the specific thickness being applicationdependent. SiN and AlGaN share the same anion and, as a result, producea transition layer between the Si₃N₄ layer 120 and the AlGaN barrierlayer 118 that has a very low density of interfacial states, e.g.,expected to be less than 1×10¹¹/cm².

As shown in FIG. 3, after the Si₃N₄ layer 120 has been grown, part ofthe Si₃N₄ layer 120 is oxidized in a steam/wet rapid thermal oxidationprocess to form a SiO₂ layer 122 that lies on the remaining Si₃N₄ layer120. In the present invention, the combination of the Si₃N₄ and SiO₂layers form a gate insulation layer 124 of the transistor which has, forexample, a Si₃N₄ layer that is 64 Å thick and a SiO₂ layer that is 128 Åthick. The oxidation of the Si₃N₄ layer 120 produces a transition layerbetween the Si₃N₄ layer 120 and the SiO₂ layer 122 that also has a verylow density of interfacial states.

As shown in FIG. 4, following the formation of SiO₂ layer 122, themethod completes the formation of GaN MOSFET 100 by forming a metal gateregion 130, a metal source region 132, and a metal drain region 134 in aconventional fashion, e.g., using titanium aluminum contacts, followedby the conventional formation of an overlying passivation layer. Themetal gate region 130 is formed to touch the SiO₂ layer 122 of gateinsulation layer 124. The metal source 132 and metal drain regions 134are formed to make an ohmic contact with the GaN channel layer 116 andthe AlGaN barrier layer 118.

As noted above, the AlGaN of the barrier layer and the GaN of thechannel layer have different band gaps, and are conventionally formed toinduce a two-dimensional electron gas (2DEG) that lies at the junctionbetween the AlGaN barrier layer and the GaN channel layer and extendsdown into the GaN channel layer.

As further noted above, the 2DEG, which functions as the “channel” ofthe transistor, produces a high concentration of electrons which causesa conventionally-formed GaN MOSFET to be a depletion mode device(nominally on when zero volts are applied to the gate of the device andthe source and drain regions are differently biased).

Thus, to form GaN MOSFET 100 shown in FIG. 4 as an enhancement-modedevice (nominally off when zero volts are applied to the metal gateregion 130, and the metal source region 132 and the metal drain region134 are differently biased), the AlGaN barrier layer 118 must be madethin enough (e.g., a few nm thick) so that when zero volts are appliedto the metal gate region 130 (and the metal source region 132 and themetal drain region 134 are differently biased) substantially noelectrons are present in the 2DEG region, and when a voltage thatexceeds a threshold voltage is a applied to the metal gate region 130(and the metal source region 132 and the metal drain region 134 aredifferently biased), electrons accumulate in the 2DEG region and flowfrom the metal source region 132 to the metal drain region 134.

FIGS. 5-9 show a series of cross-sectional views that illustrate anexample of a method of forming an enhancement-mode GaN MOSFET 500 inaccordance with an alternate embodiment of the present invention. Asshown in FIG. 5, the alternate method of the present invention alsoutilizes a conventionally-formed semiconductor substrate 510. As withsubstrate 110, substrate 510 can also be implemented as an insulatingsubstrate or with a highly resistive material such as silicon (e.g.,<111>), sapphire, or silicon carbide.

As further shown in FIG. 5, the alternate method of the presentinvention begins by forming an epitaxial layer 512 on substrate 510 inthe same manner that epitaxial layer 112 was formed (in a MOCVD reactorusing a conventional process). As a result, epitaxial layer 512 includesan undoped AlGaN buffer layer 514, an undoped GaN channel layer 516, andan undoped or n-doped AlGaN barrier layer 518 (or optionally an undopedor n-doped InAlGaN barrier layer 518). The AlGaN buffer layer 514, inturn, includes a number of undoped AlGaN layers with different aluminumcompositions that are used to mitigate stress.

However, unlike GaN MOSFET 100, the AlGaN barrier layer 518 is formed tohave a conventional (depletion-mode) thickness and, as a result, inducesthe formation of a two-dimensional electron gas (2DEG) that lies at thejunction between the AlGaN barrier layer 518 and the GaN channel layer516 and extends down into the GaN channel layer 516. The 2DEG that liesat the junction between the AlGaN barrier layer 518 and the GaN channellayer 516 produces a high concentration of electrons.

As shown in FIG. 6, in accordance with the present invention, afterepitaxial layer 512 has been formed, a mask 520, such as a layer ofSiO₂, is formed and patterned on the top surface of the AlGaN barrierlayer 518. Once mask 520 has been formed, the regions exposed by themask 520 are dry etched. The dry etch can stop above, at, or below alowest level of the 2DEG that lies at the top surface of GaN channellayer 516. (FIG. 6 illustrates the dry etch stopping just below thelowest level of the 2DEG.)

As further shown in FIG. 6, the dry etch produces an intermediate MOSFETstructure 522 that has an exposed region 524. Following the dry etch,the intermediate MOSFET structure 522 is next baked in H₂ and NH₃ in theMOCVD reactor to repair damage to the lattice that was caused by the dryetch. In other words, the intermediate MOSFET structure 522 is bakedafter the dry etch without removing the intermediate MOSFET structure522 from the MOCVD reactor.

As shown in FIG. 7, after the intermediate MOSFET structure 522 has beenbaked, a thin undoped or n-doped AlGaN barrier film 526 (or optionally athin undoped or n-doped InAlGaN barrier film 526) is epitaxially grownon the exposed region 524. A top surface of the thin AlGaN barrier film526 can lie above, at, or below a lowest level of the 2DEG. (FIG. 7illustrates the top surface of the AlGaN barrier film 526 lying at thelowest level of the 2DEG.) The thin AlGaN barrier film 526 has athickness that is less than a largest thickness of the AlGaN barrierlayer 518.

Once the thin AlGaN barrier film 526 has been grown, a Si₃N₄ layer 530is epitaxially grown on the thin AlGaN barrier film 526 directly in thesame MOCVD reactor as the thin AlGaN barrier film 526 using SiH₄ andNH₃. In other words, the Si₃N₄ layer 530 is epitaxially grown after thethin AlGaN barrier film 526 is grown without removing the structure withthe thin AlGaN barrier film 526 from the MOCVD reactor. (As shown inFIG. 7, the Si₃N₄ layer 530 also grows on the side walls of the AlGaNbarrier layer 518 and on the SiO₂ mask 520.)

The Si₃N₄ layer 530 is preferably grown to have a thickness ofapproximately 10-100 nm over the thin AlGaN film 526, with the specificthickness being application dependent. As before, the process produces atransition layer between the Si₃N₄ layer 530 and the thin AlGaN barrierfilm 526 that has a very low density of interfacial states, e.g.,expected to be less than 1×10¹¹/cm².

As shown in FIG. 8, following the growth of the Si₃N₄ layer 530, a partof the Si₃N₄ layer 530 is oxidized in a steam/wet rapid thermaloxidation process to form a SiO₂ region 532 that lies on a Si₃N₄ region534 which, in turn, lies over the thin AlGaN barrier film 526. Asfurther shown in FIG. 8, the AlGaN barrier layer 518 lies laterallyadjacent to the Si₃N₄ region 534. (The oxidation process also oxidizesthe Si₃N₄ layer 530 that lies over the SiO₂ mask 520, thereby increasingthe thickness of the SiO₂ mask 520.)

In the present invention, the combination of the Si₃N₄ region 534 andthe SiO₂ region 532 forms a gate insulation layer 536 that lies over thethin AlGaN film 526 which has, for example, a Si₃N₄ region that is 64 Åthick and a SiO₂ region that is 128 Å thick. As before, the oxidation ofthe Si₃N₄ layer 530 produces a transition layer between the Si₃N₄ region534 and the SiO₂ region 532 that also has a very low density ofinterfacial states.

As shown in FIG. 9, following the formation of SiO₂ region 532, themethod completes the formation of GaN MOSFET 500 by forming a metal gateregion 540, a metal source region 542, and a metal drain region 544 in aconventional fashion, e.g., using titanium aluminum contacts, followedby the conventional formation of an overlying passivation layer. Themetal gate region 540 is formed to touch SiO₂ region 532 of gateinsulation layer 536. The metal source 542 and metal drain regions 544are formed to make an ohmic contact with the GaN channel layer 516 andthe AlGaN barrier layer 518.

Thus, GaN MOSFET 500 shown in FIG. 9 is formed as an enhancement-modedevice (nominally off when zero volts are applied to the metal gateregion 540 and the metal source region 542 and the metal drain region544 are differently biased) by forming the AlGaN barrier film 526 to bethin enough (e.g., a few nm thick) so that when zero volts are appliedto the metal gate region 540 (and the metal source region 542 and themetal drain region 544 are differently biased) substantially noelectrons accumulate directly under the gate insulation layer 536 andthe metal gate region 540, and when a voltage that exceeds a thresholdvoltage is a applied to metal gate region 540 (and the metal sourceregion 542 and the metal drain region 544 are differently biased),electrons accumulate directly under the gate insulation layer 536 andthe metal gate region 540 and flow from the metal source region 542 tothe metal drain region 544.

One of the advantages of the present invention is that the Si₃N₄ portionof the SiO₂/Si₃N₄ gate insulation layer significantly reduces theformation of interface states at the junction between the gateinsulation layer and the AlGaN barrier layer (or optional InAlGaNbarrier layer). Significantly reducing the number of sites whereelectrons can be trapped significantly improves the long-termreliability of the GaN devices.

A further advantage of the present invention is that by utilizing SiO₂as the capping layer of the SiO₂/Si₃N₄ gate insulation layer, thepresent invention has the lowest leakage current and a threshold voltageas high as 2.5 volts (i.e., SiO₂ has a bandgap Eg of 9 eV and a ΔEc toAlGaN that can be as high as 2.5 eV).

FIG. 10 shows a band diagram that illustrates the leakage current inaccordance with the present invention. As shown in FIG. 10, the bandlineup shows that there is limited tunneling in the gate oxide due tothe low density of interface states and the wide band gap of SiO₂. Inaddition, the effective ΔEc from SiO₂ to AlGaN is greater than 2 eV witha threshold voltage Vt that is greater than 2V.

It should be understood that the above descriptions are examples of thepresent invention, and that various alternatives of the inventiondescribed herein may be employed in practicing the invention. Therefore,it is intended that the following claims define the scope of theinvention and that structures and methods within the scope of theseclaims and their equivalents be covered thereby.

1. A method of forming a transistor comprising: forming a barrier layer, the barrier layer including AlGaN; forming a layer of Si₃N₄ that touches the barrier layer; forming a layer of SiO₂ that touches the layer of Si₃N₄; and forming a metal gate that touches and lies over the layer of SiO₂.
 2. The method of claim 1 wherein: the barrier layer is epitaxially grown in a reactor; and the layer of Si₃N₄ is epitaxially grown in the reactor after the barrier layer is grown without removing the barrier layer from the reactor.
 3. The method of claim 2 wherein the layer of SiO₂ is formed to touch the layer of Si₃N₄ by oxidizing a portion of the layer of Si₃N₄.
 4. The method of claim 3 and further comprising forming spaced-apart metal source and drain regions that touch the barrier layer.
 5. The method of claim 4 wherein the barrier layer further includes indium.
 6. The method of claim 4 and further comprising forming a channel layer before the barrier layer is formed, the channel layer including GaN, a top surface of the channel layer touching a bottom surface of the barrier layer, the channel layer including a two dimensional electron gas that touches the top surface of the channel layer.
 7. The method of claim 6 and further comprising selectively etching the barrier layer to form an exposed region before the layer of Si₃N₄ is formed.
 8. The method of claim 7 and further comprising forming a barrier film to touch the exposed region before the layer of Si₃N₄ is formed, the barrier film including AlGaN.
 9. The method of claim 8 wherein the layer of Si₃N₄ is formed to touch and lie over the barrier film.
 10. The method of claim 6 and further comprising selectively etching the barrier layer and the channel layer to form an exposed region before the layer of Si₃N₄ is formed.
 11. The method of claim 10 and further comprising forming a barrier film to touch the exposed region before the layer of Si₃N₄ is formed, the barrier film including AlGaN.
 12. The method of claim 11 wherein the layer of Si₃N₄ is formed to touch the barrier film.
 13. The method of claim 12 wherein the barrier layer further includes indium, and the barrier film further includes indium.
 14. A transistor comprising: a barrier layer, the barrier layer including AlGaN; a layer of Si₃N₄ that touches the barrier layer; a layer of SiO₂ that touches and lies over the layer of Si₃N₄; and a metal gate that touches the layer of SiO₂, and lies above the layer of SiO₂, and the layer of Si₃N₄.
 15. The transistor of claim 14 and further comprising spaced-apart metal source and drain regions that touch the barrier layer.
 16. The transistor of claim 15 wherein the barrier layer further includes indium.
 17. The transistor of claim 15 and further comprising a channel layer that touches and lies below the barrier layer, the channel layer including GaN, the channel layer including a two dimensional electron gas that touches the top surface of the channel layer.
 18. The transistor of claim 17 and further comprising a barrier film that touches and lies below the layer of Si₃N₄, the barrier film having a thickness that is less than a largest thickness of the barrier layer, the barrier film including AlGaN.
 19. The transistor of claim 18 wherein the barrier layer lies laterally adjacent to the layer of Si₃N₄.
 20. The transistor of claim 19 wherein the barrier layer further includes indium. 